Rishabh Agarwal
CPU Power engineer
- Role
- Cpu Power Engineer at Arm
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Rishabh Agarwal
My interest is in everything related to power optimization/management of a IP/SOC/system/rack.My background is in physical design, STA. RTL-to-GDSII – worked on nodes from 90nm to present sub 10 nm cutting edge nodes.Power estimation/analysis methodologies for RTL,netlist,perf/watt tradefoff analysis, what-if analysis for new features. Power modeling / outlier analysis for power models.Collaboration with architects,PD and Post-Si teams to optimize power of the design.Power tracking/optimization at IP level -CPU to SoC. Knowledge of server/mobile CPU\'s, AI accelerators.
Experience
Cpu Power Engineer
Sep 2024 — Present · Austin, TX, US
Education
Manipal Institute of Technology
Bachelor of Engineering (B.E.), Electronics and Communications Engineering
2008 — 2012
North Carolina State University
Master of Science (M.S.), Computer Engineering
2015 — 2017
Skills
- Circuit Design
- Synopsys Tools
- C
- Vlsi
- Vhdl
- Simulations
- Algorithms
- Physical Design
- Microcontrollers
- Cmos
- Integrated Circuits (Ic)
- Modelsim
- Asic
- Application-Specific Integrated Circuits (Asic)
- Physical Verification
- Lvs
- Cadence
- Spice
- Tcl
- Rtl Design
- Semiconductors
- Soc
- Cadence Virtuoso
- Verilog
- Unix
- Drc
- Shell Scripting
- Cadence Encounter
- C++
- Soc Floorplanning
- Layout Versus Schematic (Lvs)
- Redhawk
- Integrated Circuit Design
- System on a Chip (Soc)
- Very-Large-Scale Integration (Vlsi)
- Perl
- Eda
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