Ragam Veeraiah
Vlsi Design and Verification Trainee @Vlsi First
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WORK HISTORY
Vlsi Design and Verification Trainee @Vlsi First
Hyderabad, IN
Design Responsibilities- RTL Design: Create Register Transfer Level (RTL) code using languages like Verilog or VHDL- Architecture Implementation: Translate system-level specifications into hardware architecture- Synthesis & Timing Analysis: Convert RTL to gate-level netlists and ensure timing constraints are met- Power Optimization: Design for low power consumption without sacrificing performance- Tool Usage: Work with EDA tools like Synopsys, Cadence, or Mentor Graphics. Verification Responsibilities- Testbench Development: Build environments using SystemVerilog and UVM to simulate chip behavior- Functional Verification: Ensure the design meets all functional requirements through simulation and debugging- Coverage Analysis: Use metrics like code and functional coverage to assess test completeness- Regression Testing: Run repeated tests to catch bugs introduced by design changes- Bug Tracking & Debugging: Identify, isolate, and fix design flaws before tape-out.
ABOUT RAGAM VEERAIAH
Hi there I have always been interested in VLSI in general, which led me to explore a lot of things under it.I am always curious about how a square centimetre comprises millions of devices. Technical Proficiencies Include:HDL: VerilogHVL: SystemVerilogVERIFICATION METHODOLOGY: Constraint Random Coverage Driven-Verification | Assertion Based Verification - SVATB Methodology: UVM( Universal Verification Methodology)EDA TOOLS:Mentor Graphics-QuestasiMDOMAIN: ASIC/FPGA Front-end Design and VerificationProtocols : AHB(LITE), I2C.OPERATING SYSTEMS: Linux.CORE SKILLS:[RTL Coding using Synthesizable constructs of Verilog | FSM based design Simulation | CMOS Fundamentals Code Coverage | Functional Coverage |Synthesis | Static Timing Analysis | Assertion Based Verification using System Verilog Assertions]
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