Radhakrishnan

Senior Principal AE at Cadence Design Systems

Role
Senior Principal Ae at Cadence
Location
Austin, TX, US
LinkedIn followers
500 followers

About Radhakrishnan

Competent, diligent and result-oriented professional, offering 15 years of semiconductor industry experience in IC design engineering. Action driven and well-focused Physical Implementation staff engineer with expertise in Synthesis, Static Timing Analysis and DFT for complex ASICs/SOCs in advanced process technology nodes.Proven ability in team skills and capable of performing in a dynamic work environment, excellent time management skills, strong analytical ability and problem-solving skills to tackle difficult challenges. Demonstrated active interest and ability to enhance new functional skills. Facilitator of direct and open communication diversity of opinion and debate. Ability to work independently and efficiently work with both internal and external teams.Core Specialties: IC Physical Implementation Staff engineer. • RTL Physical Synthesis and Floor-planning.• Static Timing analysis and timing closure.• DFT implementation and verification.• Proficiency in TCL/Perl scripting. • Spyglass Lint, DFT and CDC verification.• Formal equivalence verification.• Industry standard EDA tools.(Mentor and Synopsys) Additional Specialties Skills: • Physical design implementation.(Place, Route and CTS)• Power analysis and estimation.

Experience

  1. Senior Principal Ae

    Cadence

    Oct 2019 — Present · Austin, TX, US

    Genus and Innovus.

Education

  • National Institute of Technology, Tiruchirappalli

    BE, Electronics and communication

    1999 — 2003

  • Seshasayee Institute of Technology, Tiruchirappalli - India

    Diploma, Electrical and Electronics Engineering

    1994 — 1997

Skills

  • Perl
  • Embedded Systems
  • Eda
  • Semiconductors
  • Vlsi
  • Mixed Signal
  • Digital Designs
  • Scripting
  • Cdc
  • Rtl Design
  • Gate Level Simulation
  • Power Analysis
  • Static Timing Analysis
  • Front-End Design
  • Formal Verification
  • Logic Bist
  • Scan Insertion
  • Verilog
  • Jtag
  • Floorplanning
  • Timing Closure
  • Dft
  • Simulations
  • Ip
  • Physical Design
  • Timing
  • Verification
  • Rtl
  • Test Design
  • Logic Synthesis
  • Soc
  • Silicon Validation
  • Tcl
  • Asic
  • Bist
  • Atpg
  • Spyglass
  • Physical Synthesis
  • Testing
  • Ic

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Radhakrishnan — Senior Principal Ae at Cadence in Austin, TX, US | Unifers