Radheshyam Baviskar

About Radheshyam Baviskar

Verification Engineer with over 8 years of experience in design and verification, specializing in OVM/UVM-based environments and formal verification. Proven expertise in verifying complex subsystems such as Power Management, Display Subsystems, and System Cache Controllers. Skilled in developing comprehensive test cases, sequences, assertions, and performing coverage analysis to ensure thorough validation. Currently focused on end-to-end formal verification, contributing to the development of robust and reliable hardware systems.

Experience

1. Senior Staff Engineer

   Marvell Technology

   Sep 2022 — Present · Pune, IN

   End to end Formal Verification

Education

• Vellore Institute of Technology

  Master’s Degree, VLSI Design (MicroElectronics)

  2014 — 2016

• Sardar Patel College of Engineering (SPCE),Mumbai

  Bachelor's Degree, Electrical and Electronics Engineering

  2008 — 2012

• Centre for Development of Advanced Computing (C-DAC)

  PG Diploma, VLSI Design

  2013 — 2014

Skills

• Static Timing Analysis
• Cadence Virtuoso Layout Editor
• Synopsys Tools
• System Generator
• Cadence Virtuoso
• C
• Programming
• Vlsi
• Physical Design
• Leonardo Spectrum
• Asic
• Verilog
• Semiconductors
• Physical De
• Vhdl
• Shell Scripting
• Cadence Encounter
• Cadence Spectre
• Perl
• Embedded Systems
• Tcl
• Very-Large-Scale Integration (Vlsi)
• Java
• Matlab
• Low-Power Design
• Arm
• Clock Tree Synthesis
• Linux
• Modelsim
• Vlsi C
• System Architecture
• Nanoelectronics
• Perl Script
• Soc
• C++
• Application-Specific Integrated Circuits (Asic)
• Vlsi Cad
• Unix
• Open Verification Methodology
• Intel Architecture