Radha S Rajan
PLL design engineer at Apple
- Role
- Pll Design Engineer at Apple
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Pll Design Engineer
Aug 2019 — Present · San Francisco, CA, US
Skills
- Verilog
- Cadence Virtuoso
- Analog Circuit Design
- Vhdl
- Embedded Systems
- Matlab
- Simulations
- C++
- C
- Vlsi
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