Rachit Garg
Focused on learning !!
- Role
- Staff Physical Design Engineer at 新思科技股份有限公司
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Rachit Garg
I have over seven years of experience as VLSI physical design engineer. I have worked on Synthesis, place and route, clock tree synthesis and timing signoff in Intel 10nm, TSMC 16nm technology.
Experience
Staff Physical Design Engineer
Oct 2024 — Present · Noida, IN
Education
MEERUT INSTITUTE OF TECHNOLOGY, MEERUT
Bachelor of Technology, Electronics and Communications Engineering
2011 — 2015
Dayalbagh Educational Institute
Master of Business Administration - MBA, Human Resources Management/Personnel Administration, General
Skills
- Shell Scripting
- Low-Power Design
- Scripting Tcl
- Microsoft Office
- Static Timing Analysis
- Makefile
- Ip Tagging & Ip Resue
- Physical Design
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