Rachana Chauhan
ASIC Physical Verification Engineer at Google | Ex-Qualcomm
- Role
- Physical Verification Engineer at Google at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Rachana Chauhan
Rachana Chauhan is currently working as Silicon Physical Design Engineer at Google. Before joining Google, I worked as Senior lead Engineer in SOC Physical Verification team at Qualcomm India Private Limited, Noida.I am having experience of approx 8 years after Mtech. Have been part of 18 successful tape outs in my career.My work responsibilities are:Hands on experience on Physical Verification of 11nm, 10nm, 7nm,5nm 4nm,3nm technology nodes.Experience of full chip & block level run and analysis.Deep Knowledge of LVS, DRC, ERC, Soft check, PERC, CNOD,DFM, Antenna, Density etc.Hands on experience on physical verification tool Calibre for all PV checks. Good working knowledge of Innovus tool. Worked on physical verification for multiple no of critical blocks (HM) and worked in SOC PV team for full chip PV convergence.Full ownership of PERC checks/LVS/CNOD checker for full chip/SOC flat.Understanding of ASIC flow (RTL to GDSII) and the stages involved in physical design flow.Good knowledge of TCL programming. Before Joining Qualcomm, I worked for approx. 5 years in Jindal Steel and Power Ltd. as Assistant Manager in Control & Instrumentation department from July 2010 to March 2015.
Experience
Physical Verification Engineer at Google
Aug 2022 — Present · Bengaluru, IN
Education
Motilal Nehru National Institute of Technology (MNNIT), Allahabad
M.TECH
Kamla Nehru Institute of Technology, Sultanpur
B.TECH
2006 — 2010
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