Raju Agarwal
AMD | Ex-Intel
- Role
- Sr Silicon Design Engineer at AMD
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Raju Agarwal
STA Engineer at AMD, where I am responsible for synthesis, constraints development & verifying constraints using Design Compiler, PrimeTime, Fishtail, TCM, and Excellicon. At Intel owned Sub-System timing and PNR. Designed High frequency Global clock in multiple IPs also.
Experience
Sr Silicon Design Engineer
May 2024 — Present · Bengaluru, IN
Tape-out 5 -AMD, BangaloreI am working on constraints development using Design Compiler and PrimeTime, and performed constraints verification using Fishtail and TCM while collaborating closely with RTL,DFT & PD teams. I am also responsible for SoC constraints equivalence using TCM and Excellicon, where I identified frequency mismatch while SoC integration, enabling timely constraint corrections and smoother convergence.
Education
Indian Institute of Technology, Guwahati
Master's degree, M.Tech in VLSI
Heritage Institute of Technology
B.Tech, Electronics and Communications Engineering
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