R Pawan Kumar

About R Pawan Kumar

ExperienceOver 8 years in the semiconductor industry, besides 1-year internship in a semiconductor laboratory, Dept. of Space, Govt. of India.Technical Expertise:• Hands-on experience with advanced TSMC and Samsung chip design processes, including 3nm, 4nm, 5nm, 7nm, 11nm, and 14nm technologies.• Strong knowledge of CMOS fundamentals and the ASIC design flow from RTL to GDSII, encompassing floorplanning, power planning, placement, CTS, and routing.• Proficient in planning and executing block-level PNR (Netlist to GDSII).• Expertise in timing closure at both block and SoC levels.• Handeled signingoff activities LEC, EMIR, PVR, QOR (STA)• Expertise in timing closure at both block and SoC levels• Skilled in managing low power and congested designs.Project Management:Successfully handled multiple projects throughout the PNR flow and tape-out activities.Tool Proficiency:Extensive experience with ICC2, Primetime, providing manual ECOs, ICV Workbench, Redhawk, and Tweaker tools.Automation Skills:Proficient in automation using Perl, TCL, and Python scripting.

Experience

1. Asic Physical Design Senior Staff Engineer

   新思科技股份有限公司

   Feb 2025 — Present

   SERDES-IP Design Experience: Worked on multiple designs in 3nm, 5nm, and 7nm technologies using the latest TSMC processes.PNR Flow Execution:Executed complete PNR flow, including floorplanning, robust power planning, custom CTS plans for high-frequency hierarchies to minimize future ECO cycles while ensuring power optimized.Timing Constraints and QoR: Comprehended timing constraints from designers, achieving superior and faster Quality of Results (QoR). Internal Timing Path Analysis: Analyzed internal timing paths, addressed constraint issues, tuned clocks for skew balancing, generated ECOs for critical paths, and conductedthorough analysis for min-max conflict paths across different corners. Performed crosstalk analysis, TDRC reviews, and resolved physical DRCs.High-Frequency Clock Management:Managed multiple high-frequency clocks within a single design, ensuring timing closure and power integrity

Education

• Kendriya Vidyalaya

  SSC, As per the CBSE Board

  2007 — 2008

• Jawaharlal Nehru Technological University

  Bachelor's Degree, Electronics and Communications Engineering

  2010 — 2014

• Kakatiya Public School

  Intermediate, As per the CBSE Board (MPC)

  2009 — 2010

• Centre for Development of Advanced Computing (C-DAC)

  Master’s Degree, VLSI Design

  2014 — 2016

Skills

• Ir Drop Analysis
• Clock Tree Synthesis
• Gds
• C
• Rtl Design
• Very-Large-Scale Integration (Vlsi)
• Static Timing Analysis
• Cadence Virtuoso
• Application-Specific Integrated Circuits (Asic)
• Crosstalk
• Verilog
• Ocv
• Floorplanning
• Physical Design
• Primetime
• Clock
• Logic Synthesis
• Cadence Encounter