Channakeshava Ranganatha
Interim Engineering Intern at Qualcomm || Actively Seeking Fall\'25 Co-Op Opportunities || MSEE at CSULB || ASIC/RTL Design, Design Verification, DFT, DFx Validation
- Role
- Interim Engineering Intern at Qualcomm
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Channakeshava Ranganatha
Currently pursuing Master\'s in Electrical Engineering at California State University. Long Beach specializing in VLSI and Computer Architecture. Research Interests: Full Cycle Silicon Chip Design Interested in job roles involving Design Verification, DFX Validation, ASIC Design (RTL) Engineer Previous role: Design Verification, DFX Validation Engineer Technology Nodes: Intel - 7nm, 10nm Tools: Mentor Graphics, MATLAB, Synopsys VCS Verdi Scripting: PERL, Python and SKILL coding Apart from this, I\'m a quick learner and adaptable to any projects related to my domain which covers my strength and talent as well.
Experience
Interim Engineering Intern
Jun 2025 — Present · Santa Clara, CA, US
Education
Sri Krishna Institute Of Technology, Bangalore
Bachelor of Engineering - BE
2016 — 2020
California State University, Long Beach
Master of Science - MS
2024 — 2025
Kendriya Vidyalaya (KV)
SSC
2004 — 2014
Seshadripuram Pre-University College - India
Intermediate
2014 — 2016
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