Qiuchen Y.

About Qiuchen Y.

10+ years of professional experience in physical design (from netlist to tape-out) for a highly complex SOC utilizing state of the art process technology:• Execution on TSMC 3/5/7nm tape-out for Broadcom SoC• Execution on Intel 10nm tape-out for 5G wireless base station SoC Snow Ridge• Execution on TSMC 28nm tape-out for Fabu AI autonomous driving SoC• Work on PD construction & analysis flows and methodology on 5/7/10/14/22/28nm• Manage block and full-chip level/SoC physical implementation and QoR (power, timing, area), developed multiple hierarchical methodology from Synthesis, Place & Route to PT/DMSA• Experience in: ASIC physical design, digital design and/or physical design flows (synthesis, place and route, STA, DFT, formal verification, power analysis, power intent (UPF/CPF), and IR/EM analysis.• Ability to multi-task and flexibility to work in global environment/teams with Good communication skills and strong motivation, Strong analytical & Problem solving skills

Experience

1. Ic Design Engineer

   Broadcom

   Aug 2019 — Present · Irvine, CA, US

   Chip level RTL to GDS implementation and HSIP multi-million cell block PnR and tapeout in most advanced technology nodes-Floorplan with complex data flow and pin assignment, Analog IP-Bump/Pad-ring planning and RDL routing-Chip clock tree design and planning-Chip Redhawk analysis for IR/EM-Physical verification sign-off with DRC/LVS/ANT/ERC

Education

• Beijing University of Technology

  Bachelor’s Degree, Electronic Science and Technology

  2006 — 2010

• The George Washington University

  Master’s Degree, Computer Engineering

  2010 — 2012