Pushpendra Pal Singh
Lead Design Engineer @Cadence Design Systems l Design Verification , Serdes ,UCIe and Chiplets
- Role
- Lead Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Pushpendra Pal Singh
9 year\'s of experience in verification using system verilog and UVM…
Experience
Lead Design Engineer
Oct 2023 — Present · Bengaluru, IN
Education
Meerut Institute of Engineering and Technology(MIET)
B.tech
2009 — 2013
Skills
- Microsoft Word
- Electronics
- C
- Microsoft Office
- Digital Electronics
- Research
- Photoshop
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