Pushkar Upadhye

About Pushkar Upadhye

Experienced in Architecture, Logic design, Timing Closure, Pre-Silicon Debug and Post Silicon Bring-up development activities. I have leveraged past experience in logic design, verification, structural design and post silicon verification in ideating and providing solution to peers and mangers during product execution.Ability to counsel project and program management on scheduling, identifying execution risks and providing ideas for mitigating those risk to achieve timely executionGood understanding of technology issues from both the front end design and physical design perspectives. CORE COMPETENCIES• Architecture development • Micro-architecture • Logic and RTL design• Design Verification • Silicon Bringup • Project Planning and Execution • Physical Design, Timing Closure • Application support for Sales • Technical support for customers

Experience

1. Senior Principal Engineer

   Marvell Technology

   Apr 2022 — Present · Pune, IN

   Senior Principal Engineer in the CCS (Custom Compute and Storage) business unit in Marvell. Micro-architecture and Design of Virtualization Management block in Data Path Processor (Octeon DPU)Responsible for Architecture and Design of on chip security infrastructure for CXL and PCIE controllers.Designing of debug infrastructure for on chip FibreChannel frame acquisition and transfer to the host memory.

Education

• Loyola High School and Junior College

  12th Grade, Science

  1990 — 1992

• Vishwakarma Institute Of Technology

  Bachelor of Engineering - BE, Electrical and Electronics Engineering

• Savitribai Phule Pune University

  B.E, Electronics

  1992 — 1996