Pushkar Tawade

About Pushkar Tawade

Overall 15+ Years experience in VLSI and Embedded Industry- Worked as Test Chip Logic lead for Memory TC, Mixed Signal PHY TC at Intel primarily on 18A and Intel3 tech nodes- Worked on cutting edge Mobile/Wearable and Base station SoC Designs at Qualcomm- Developed and Managed FPGA Based Active DAS Hub Solution for 5G Network at Samsung Communication R&D- Experienced in CPRI, FEC, SERDES(10G, 25G line, 40G, 100G+ Channel Bonded), MIPI C-PHY, D-PHY, DDR PHY, Ethernet MAC, Flow Control, High Speed Interface Network System Designs Mixed Signal IP design- Expertise in Multiple FPGA & Processor based End to End Product Development- 9+ years of experience to Lead FPGA & ASIC RTL Design Team.Experienced working with cross-functional and geographically isolated teams. Adaptive to multi-tasking. Endowed with quick learning and decision making skills.

Experience

1. Principal Engineer

   Marvell Technology

   Oct 2025 — Present · Bengaluru, IN

   Working as a Digital IC Design Engineer

Education

• Rajarambapu Institute of Technology, Sangali

  B.E, Electronics and Telecommunication Engineering

  2005 — 2009

• CDAC ACTS

  DVLSI, VLSI Design

  2010 — 2010

• S.M. Highschool, Kankavali

  S.S.C

  1998 — 2003

• S.M.Junior College of Science and Commerce, Kankavali

  H.S.C., Physics, Chemistry, Biology, Mathematics

  2003 — 2005

Skills

• Modelsim
• Vhdl
• Functional Verification
• System Design
• Fpga Prototyping
• Rtl Design
• Microcontrollers
• Fpga
• Asic
• Xilinx
• Systemverilog
• Integrated Circuit Design
• Xilinx Ise
• Rtl Development
• Static Timing Analysis
• Ethernet
• C
• Verilog
• Application-Specific Integrated Circuits (Asic)
• Altera Quartus
• Field-Programmable Gate Arrays (Fpga)