Purna Chandra Sekhar

About Purna Chandra Sekhar

Experience in Analog/Mixed signal IC layout.Experience in the layout of IC functional blocks such as>Amplifiers, LDO, high speed LS, Opamp,BG reference, Digital logic blocks, Regulators in oscillator. Good understanding of Layout Design techniques:>Signal Flow, Matching, WPE effects, LOD, Shielding, Electro-Migration, Parasitic elements, Cross Talk, Antenna Rules and Solutions, Latch up and delay reduction.> Good understanding about EM, IR and hotspot analysis and fixes.> Good understanding on layout construction, verification, analysis and fixesGood in LVS, DRC and ERC debug including densitychecks in tools: Calibre, Synopsys ICV.Good understanding of CMOS and Finfet technologies.Technology Nodes :>3nm FinFet (Samsung)>4nm FinFet (Samsung)>12nm FinFet (GF)>22nm FDSOI(GF)>28nm CMOS (TSMC) Layout and Verification Tools Used:>Cadence Virtuoso L, XL>Synopsys Custom Compiler Knowledge in Linux Shell,TCL,Perl scripting, Basics of SKILL scriptingEfficient in layout construction by using Clones, half cellAble to work independently as well as with the team. Good communication skill, Good problem-solving skills, Good documentation and presentation skills.Good knowledge on Microsoft Office applications such as Microsoft Excel, Microsoft PowerPoint.

Experience

1. Deg Layout Engineer

   Micron Technology

   Jun 2022 — Present · Hyderabad, IN

Education

• PRASAD V POTLURI SIDDHARTHA INSTITUTE OF TECHNOLOGY, Vijayawada

  Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering

  2013 — 2017

• BITS Pilani Work Integrated Learning Programmes

  Master of Technology - MTech, Microelectronics