Punyasloka Bal
Engineering Manager at NVIDIA (Physical Design)
- Role
- Engineering Manager (Physical Design) at NVIDIA
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
Experience
Engineering Manager (Physical Design)
Jan 2024 — Present · Bengaluru, IN
Education
Indian Institute of Technology, Kanpur
Master of Technology (M.Tech.), vlsi
2011 — 2013
Skills
- Drc
- Verilog
- Pspice
- Lvs
- Power Electronics
- Device Modeling
- Xilinx
- Fpga
- Asic
- Layout Design
- Cadence Virtuoso
- C++
- Analog Circuit Design
- Pex
- Vhdl
- C
- Vlsi
- Circuit Design
- Matlab
- Mentor Graphics Tool
- Digital Electronics
- Synopsys Tools
- Digital Ic Design
- Soi
- Semiconductors
- Integrated Circuit Design
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