Puneet Ahuja

About Puneet Ahuja

Summary/Strengths: Experienced Technology professional in Front-end Design Verification with two decades of rich experience.• Leading a team of significant size responsible for verification of DDR PHY. Responsible for verification sign-off for all DV domains including RNM, AMS Cosims, Formals and Firmware-HW co-verification.• Deeply involved in deciding verification strategy, test planning, testbench architecture, DV methodology, defining flow and process, signoff criteria.• One point of contact to roll up DV status summary to senior executives.• In the past, have led DV of Serdes/PHY IPs – 112G HS, USB2.0, MIPI DPHY1.2, ADC.• Experienced in building teams of significant size from the scratch. • Led cross site and cross domain collaboration with focus towards process and quality improvement.• Highly capable in handling DV execution for multiple IPs at the same time with focus on timely completion of DV to secure the tapeout with quality.• Expert in matric driven functional verification for IP and testchip.• Result oriented strategic planning.• Low power verification using UPF/CPF• Efficient in providing post silicon support to validation team.• Familiar(certified) with Functional Safety standard ISO 26262

Experience

1. Sr Manager, Silicon Design Engineering

   AMD

   Sep 2021 — Present · Bangalore Urban, IN

Education

• Dr. A.P.J. Abdul Kalam Technical University

  B.Tech, Electronic And Communication

  2000 — 2004

• Centre for Development of Advanced Computing (C-DAC)

  Advance Diploma in VLSI System Design, VLSI

  2004 — 2005

Skills

• Open Verification Methodology
• Vlsi
• Static Timing Analysis
• Vmm
• Asic
• Modelsim
• Verilog
• Rtl Design
• Soc
• Ncsim
• Jtag
• Debugging
• Systemverilog
• Specman
• Gigabit Ethernet
• Functional Verification
• Tcl