Pulkit Saraf
Principal Design Engineer at Cadence
- Role
- Principal Design Engineer at Cadence
- Location
- Pune District, MH, IN
- LinkedIn followers
- 500 followers
About Pulkit Saraf
Strong analog circuit design fundamentals.*Worked on TSMC 3nm and Intel 7nm,10nm etc. technology nodes.*Experience in BGR,LDO\'s & Power management block designs and sub circuits like OPAMP\'s, Comparators, Level Shifter, Current Mirrors and basic building Blocks.*Good Experience in Design and Verification of Analog Circuits meeting specification across PVT Corner conditions & MC simulations.*Knowledge on basic Layout techniques.*Worked on DC-DC converter.*Good knowledge of design for reliability like Aging, EOS, EMIR and HV.*Knowledge on basics of programming languages like unix, c++,verilog & verilog-A.*Familiar with customer release files like gds, lef, gds, hv dataset and libs.*Familiar with QR Analysis (QRE).*Familiar with CAD tools like Cadence - Virtuoso, Spectre, Hspice etc.*Got Quarterly Recognition for the LDO design work during Mar-2021
Experience
Principal Design Engineer
Jan 2026 — Present
Education
Shri G S Institute of Technology & Science
Master of Technology (M.Tech.), VLSI Design
2014 — 2016
C-DAC, ACTS, Pune
PG-DVLSI, VLSI Design
2016 — 2017
Chamelidevi Group of Institutions, Indore
Bachelor of Engineering (BE), Electronics and communication
2009 — 2013
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