Sathya Pavan

About Sathya Pavan

A. Programming skills using Verilog, VHDL.B. Hands on experience in developing RTL for Radio Receivers, 802.11 b/n wireless protocols. C. Hands on experience in Digital Design Methodologies and FSM based design.D. Experience in Prototyping the Designs on FPGA platformE. Complete Flow in FPGA from RTL design to Bit stream generation.G. Optimising the Verilog RTL to reduce Floor Area size in ASIC designs.H. Working on Wireless technologies like 802.11b/n for low-power wifi solutions.I. Design of Hardware accelerators for processor-based SoC.Specialties: Verilog RTL Design, VHDL.FPGA Prototyping for ARM based designs(CORTEX-R4).

Experience

1. Sr Manager

   Infineon Technologies

   Mar 2022 — Present · Bengaluru, IN

   Working on WLAN PHY RTL design for IoT products.

Education

• Sri Krishnadevaraya University

  B.Tech, Electronics and Communication

  2001 — 2005

Skills

• Perl
• Field-Programmable Gate Arrays (Fpga)
• Rtl Design
• Fpga
• Asic
• Vhdl
• Simulations
• Dsp
• Debugging
• Rtl Coding
• Arm Architecture
• Application-Specific Integrated Circuits (Asic)
• Ahb
• Digital Design
• Xilinx
• Verilog
• C
• Static Timing Analysis
• Ncsim
• Low-Power Design
• Arm
• Vlsi
• System on a Chip (Soc)
• Modelsim
• Integrated Circuit Design
• Logic Design
• Unix
• Digital Signal Processors
• Soc
• Xilinx Ise
• Simulation