Praveen Bharadwaj
SERDES
- Role
- Principal Engineer at 新思科技股份有限公司
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Praveen Bharadwaj
I am passionate about digital design and digital circuits. Currently working on PCIe7 subsystem and Eth 1.6T full stack. Design experience on UCIe and Chip to Chip communicationsAlso worked on DP/eDP high speed RX design with speed upto 8.1Gbps. Designed and implemented PI based CDRI have worked on different connectivity protocols for PHYMIPI MPHY G5, DPHY, USB2.0 PHY, HDMI RXSpecialties: Frontend digital design flow that involves vcs,xcelium, Simvision, Cadence Conformal, RC/FC synthesisSynopsys digital flow : VCS, Formality ECO flows, Spyglass Lint, SDC and CDC, Primetime STALanguages knownVerilog, System Verilog, C/C++, Perl, TCL, MATLAB, Shell scriptingIBM Clearcase, SVN, Perforce
Experience
Principal Engineer
Jun 2024 — Present · Bengaluru, IN
Education
North Carolina State University
M.S, Electrical Engineering
2008 — 2010
Visvesvaraya Technological University
B.E, Electronics and Communication
2001 — 2005
Skills
- Matlab
- Modelsim
- Simvision
- Cadence Virtuoso
- Atrenta Spyglass
- Vlsi
- Verilog
- Integrated Circuit Design
- Computer Architecture
- Rtl Design
- Asic
- Digital Signal Processors
- Cadence Rc Synthesis
- Tcl
- Cadence Encounter
- Perl
- Irun
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