Prudhvi Raj

About Prudhvi Raj

Technical Skills: Digital:Design using Verilog,RTL,Synthesis and netlist generation,Perl and Python scripting,HDL and Verification,System on Chip design,DFT, Place and route, Timing closure, Static Timing Analysis, Congestion, Design Flow, Physical Verification, Power analysis, Block level Physical Design. Analog: Cadence 6.1,modeling through simulink,Working on design of High speed low power CMOS circuits,PVT analysis,Circuits,DRC/LVS, Metal Fill Opamps, PLL\'s modeling. Tools: Cadence Virtuoso-6.1, Assura, VCS Synopsys, Design Vision, RTL compiler, Soc encounter, Encounter Timing Analysis, Matlab, Simulink, Hercule,ModelSim, MultiSim,Spice Simulation, Xilinx ISE Design, IC validator, Mentor Graphics Calibre. Languages: Verilog, SystemVerilog, C, C++, Perl, Phyton Verification Methodology : UVMSOC Protocol : APB, AHB, SPI, I2C,

Experience

1. Senior Staff Application Engineer

   Synopsys Inc

   May 2022 — Present · Mountain View, CA, US

Education

• Jawaharlal Nehru Technological University

  Bachelor's degree, Electrical, Electronics and Communications Engineering

  2009 — 2013

• San José State University

  Master’s Degree, Electrical Engineering Technologies/Technicians

  2014 — 2016

Skills

• Matlab
• Modelsim
• Static Timing Analysis
• Cadence Virtuoso Layout Editor
• Xilinx Ise
• Vhdl
• Vlsi
• Application-Specific Integrated Circuits (Asic)
• C++
• Encounter
• Timing Closure
• C
• Systemverilog
• Spice
• Physical Design
• Verilog
• Analog
• Perl
• Cadence Encounter
• Cadence
• Cmos
• Dft
• Rtl Design
• System on a Chip (Soc)
• Logic Synthesis
• Very-Large-Scale Integration (Vlsi)
• Simulink
• Rtl
• Integrated Circuit Design
• Asic
• Soc
• Digital Circuit Design