Prudhvi Raju Jidugu
Senior Associate Design & Verification Engineer @Capgemini Engineering
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WORK HISTORY
Senior Associate Design & Verification Engineer @Capgemini Engineering
Chennai, IN
EDUCATION
Andhra Polytechnic, Kakinada
Diploma
NRI Institute of Technology, Pothavarappadu (V), Agiripalli (M), Vijayawada Rural, PIN-821212(CC-KN)
Bachelor of Technology - BTech
ABOUT PRUDHVI RAJU JIDUGU
Technical Skills -• HDL - Verilog, SV, VHDL Programming• EDA Tool : Intel - Quartus Prime, Xilinx Vivado, Mentor Graphics - Questasim Microchip - Libero• Operating System - Windows, Linux• Basics of UVMCore Skills -• RTL Coding• FSM Based Design Expertise• Functional Verification• Static Timing AnalysisScripting Languages -• PythonTechnologies -• 5G O-RU Model Processing• Fronthaul Layer MappingSubject Expertise -• Digital VLSI Design• Digial ElectronicsHands-on experience in projects across the Telecom and Medical domains, demonstrating versatility and domain adaptability. Skilled in industry-standard protocols including O-RAN, Ethernet, eCPRI, AXI4. Experience in IP Integration & Verification, ensuring seamless module-level and system-level functionality.
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