Progyna Khondkar

About Progyna Khondkar

Working as Architect at Cadence Design Systems, where my responsibilities are on Xcelium Simulation and Palladium Emulation Technology, specifically on low-power design and power-aware verification. I have a PhD in Computer Architecture from Tohoku University. I have over 20 years of experience in RTL-IP design, development, integration, debug and verification in ASIC and EDA industries.My core competencies include functional part of product engineering, product development, methodology implementation. I am the owner and leader of Xcelium and Palladium Low Power products. I am also a Senior Member of a Program Committee Member of Design Automation Conference, and Design Verification Conference, USA. I have authored the only Low Power Verification Engineering book in the market, published by Springer. I also have multiple publications and patents on low power verification and design. My mission is to simplify power management architecture and debugging, and to enable efficient and reliable low power solutions for complex SoC designs.

Experience

1. Technical Program Committee Member

   Dac, The Chips To Systems Conference

   Jan 2022 — Present · CA, US

Education

• Hirosaki University

  Master's Degree, Computer and Electronics

  1999 — 2001

• The University of Texas at Austin

  Postgraduate Program in AIML, Artificial Intelligence & Machine Learning: Business Applications

• Tohoku University

  Doctor of Philosophy (Ph.D.), Computer Architecture

  2001 — 2004