Priyanshi S.
PDK Engineer| Physical Verification Expertise
- Role
- Component Design Engineer Physical Verification Pdk at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Priyanshi S.
PDK Validation Engineer with 7+ years in physical verification across advanced nodes (28nm–5nm).Expert in DRC, LVS, density checks, and parasitic extraction. Hands-on with Cadence Virtuoso, Calibre, Synopsys ICV, and automation via SKILL and shell scripting.With a Master’s in VLSI Design from Banasthali Vidyapith, contributed to advancements in semiconductor technologies, including FinFET and CMOS nodes. Demonstrated a focus on enabling robust design-to-verification workflows that drive high-performance semiconductor innovations.
Experience
Component Design Engineer Physical Verification Pdk
Dec 2020 — Present · IN
Executed comprehensive validation of Process Design Kits (PDKs) across 14nm, 10nm, and 5nm technology nodes. • Ensured layout verification, parasitic extraction, and simulation flow checks using Cadence Virtuoso and Custom Compiler. • Collaborated with cross-functional teams to enhance design accuracy and efficiency, leading to improved product reliability.
Education
Banasthali Vidyapith
Masters Degree, Vlsi Design
2015 — 2017
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