Priyanka R

About Priyanka R

Priyanka is working in Cisco as Hardware Engineer with focus on static timing analysis and timing closure. She has 6 years of prior experience in the semiconductor industry on different areas of pre-Silicon design including RTL logic, LEC, Linting, Synthesis, ULT and timing closure (STA). Good understanding of Reg Bus architecture and high speed datapath logic design. Priyanka graduated from San Jose State University in 2016 with Masters in Electrical Engineering, Digital Logic Design as majors.Area of Expertise:UVM Testbench, Functional and RTL Coverage, System Verilog Assertions in Assertion Bsed Verification methodology, Register Abstraction Layer (RAL), ASIC Design Flow, RTL coding using Verilog/System Verilog, Fullchip Simulations for functional verification, Synthesis, fullchip timing closure across different PVT, HSPICE/XA, Logical equivalence (LEC), Formal Verification, Liberate Mx Memory Characterization (timing, switching power and leakage), understanding-of operating conditions(OCV, AOCV, POCV), static timing analysis(STA) with PrimeTime, CDC, dynamic timing verification with GLS, waveform debug using Synopsys Verdi, Custom Waveviewer, Perforce, DFT

Experience

1. Sta Engineer

   Apple

   Oct 2024 — Present · Cupertino, CA, US

Education

• San José State University

  Master of Science (M.S.), Electrical Engineering

  2014 — 2016

• Vellore Institute of Technology

  Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering

  2009 — 2013

• UCSC Silicon Valley Extension

  Timing Closure in IC Design

• UCSC Silicon Valley Extension

  Practical DFT Concepts for ASICs, SoC and SiP

Skills

• C
• Matlab
• C++
• Microsoft Office
• Xilinx
• Verilog
• Photoshop
• Vhdl
• Embedded Systems
• Perl
• Modelsim
• Linux
• Xilinx Ise
• Rtl Design
• Unix
• Html
• Programming
• Windows
• Powerpoint
• Microsoft Excel
• Ni Multisim
• Python
• Testing
• Microcontrollers
• Synopsys Tools
• Set Top Box
• Clearcase
• Rtl Coding
• Cadence Virtuoso
• Vlsi
• Debugging
• Fpga
• Asic
• Simulations
• Microsoft Word
• Simulink
• Electrical Engineering
• System Verilog
• Engineering
• Logic Synthesis