Priyajit Mahata
Principal Design Engineer at Cadence
- Role
- Principal Design Engineer at Cadence
- Location
- Kolkata, WB, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Priyajit Mahata
Working on Memory Interface, Low power DDR, GPIO, I2C, I3C
Experience
Principal Design Engineer
Aug 2024 — Present · Bengaluru, IN
Working on High speed Memory Interfaces (DDR, LPDDR5/5x/6), audio interfaces
Education
Indian Institute of Technology, Kharagpur
Master of Technology (M.Tech.), Microelectronics and VLSI design
2012 — 2014
Indian Institute of Engineering Science and Technology (IIEST), Shibpur
Bachelor's degree, Electronics and Communications Engineering
2007 — 2011
Skills
- Cadence Virtuoso
- Very-Large-Scale Integration (Vlsi)
- Mixed Signal
- Analog Circuit Design
- Cmos
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.