Priyadarsini S
Component Design Engineer - Custom Layout PDK Validation
- Role
- Pdk Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Priyadarsini S
Engineer with over 4 years of successful experience in Physical Verification for Digital layouts, Custom Layout for Analog Designs and Quality Assurance on PDK. Recognized consistently for performance excellence and contributions.
Experience
Pdk Engineer
Feb 2022 — Present · Bengaluru, IN
Education
Mepco Schlenk Engineering College
Master’s Degree
2016 — 2018
Mepco Schlenk Engineering College
Bachelor’s Degree
2012 — 2016
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