Priyadarshee Sinha

About Priyadarshee Sinha

Experienced AMS Verification Engineer with a proven track record of working in the several challenging verification projects in the semiconductor industry. Proficient in Mixed Signal Verification using SV-UVM methodology, Model development, scripting languages and has sound knowledge of analog-mixed signal blocks##Mixed signal Verification (Current - 5yrs)> Analog Mixed Signal Verification and Digital mixed signal verification - Chip-Level Testplan creation & verification - Co-sims - DMS Testcase building using UVM (Universal verification methodology)> Model development for complex-Mixed signal blocks - Proficient in verilog-AMS, systemVerilog, wreal, wreal/RNM models##Automation :>PDK Validation and Automation(Shell, Perl, SKILL,TCL)##Mixed Signal Design :> Custom-design of low-proper circuits for crypto-currency> Design of comparator for High Speed, High Resolution SAR-ADC> Design of PLLTechnologies :65nm, 22nm, 14nm,7nmTools :Cadence-VirtuosoLanguages :Shell, Skill, Perl, TCL, Verilog-AMS, System Verilog, UVM

Experience

1. Sr Lead Verification Engineer

   NXP Semiconductors

   May 2022 — Present

Education

• Dr B.C Roy Engineering college

  B.TECH, Electronics & Communication

  2007 — 2011