Pritam Payra

About Pritam Payra

Physical Design Engineer**Dedicated and skilled Physical Design Engineer with one year of hands-on experience in the semiconductor industry, specializing in 28nm technology. Proficient in block-level Place and Route, I bring expertise in managing various power domains using UPF (Unified Power Format). My capabilities extend to Static and Dynamic IR extraction, ensuring optimal performance in the designs I handle.In the realm of backend STA (Static Timing Analysis), I have successfully navigated complex challenges, ensuring the precision and reliability of timing constraints. My proficiency spans a range of industry-standard EDA tools, including Synopsys\' ICC2, Primetime, Voltus, and Calibre, where I\'ve demonstrated adeptness in leveraging these tools for seamless design execution.My skill set extends beyond digital design, encompassing CMOS layout design using the Virtuoso tool. This multifaceted experience allows me to contribute holistically to the semiconductor design process, from initial layout to final implementation.My commitment to staying abreast of industry trends and continuous learning underscores my adaptability and readiness to tackle evolving challenges in the ever-dynamic field of semiconductor design. Looking forward to applying my skills and expertise to contribute to innovative and cutting-edge projects in the semiconductor domain.

Experience

1. Physical Design Engineer Contractor

   AMD

   Aug 2024 — Present

Education

• FUTURE INSTITUTE OF TECHNOLOGY

  B.Tech in Electrical Engineering

  2019 — 2023

• FUTURE INSTITUTE OF TECHNOLOGY

  Bachelor of Technology - BTech

  2019 — 2023