Rana

About Rana

At Google, as part of the PD/PDN flow development CAD team, I contribute to advancing automation for PD-related stages in the cutting-edge 2nm technology node. My work supports efficient and optimized workflows, leveraging Python and TCL for seamless process implementation. PROJECT LEADERSHIP• GKC (Gatekeeper Checker) Dashboard, PD Dashboard, RTL2GDS Dashboard Regressions and Supportingglobal design teams through multiple PNR flow stages.• Debugging and perfecting scripting for EDA tools and design requirements also releases the Dashboard ontime to time for Design Teams.EDA TOOLS• Cadence: Genus, Innovus, Voltus, Tempus, Conformal,• Synopsys: ICC-II, Design Compiler, FC_Shell, PT_Shell, InterpreterPhysical Design Implementation and Development of Automatios Expertise• RTL to GDS-II flow development and execution.• Synthesis flow execution from the scratch with EDA tool Genus.• Automation of Sanity Checks for Synthesis, formal verification, Floorplan, Place, Clock Tree Synthesis (CTS),Routing, STA, PV, and PDN stages.• Libraries configuration from scratch & setups the configuration files such as constraints, VT cells distribution, settingup dont_use_cells/dont_touch cells etc.• Design enablement, Regression development, and Design flow automations.• TCL scripting (advanced level) – flow automation, tool integration, regressions, design metric extraction, reportgeneration, dashboard logic• Shell scripting – environment setup, batch processing• Dashboard development and maintenance across multiple EDA tools• Script debugging, optimization, and performance tuningSoft Skills & Professional Competencies• Technical project leadership and mentoring.• Cross-functional and global team collaboration• Design quality optimization (QoR: Quality of Results)• Technical documentation and knowledge transfer• Problem-solving and root-cause analysis• Continuous learning and technical excellence mindset

Experience

1. Pd Cad Engieer

   Google

   Aug 2025 — Present · Bengaluru, IN

   Working with PD/PDN flow development CAD Team for the lowest tech Node 2nm and implementing the PD-related stages automation with Python and TCL.Developed ECO flow solutions and supported DRV closure in Innovus for advanced-node programs.• Implemented net-length control strategies for both data and clock nets using buffer and clock-buffer based approaches.• Applied always-on buffer handling for power-domain net constraints.• Defined fanout-based buffering strategies using single-buffer, partitioned-buffer, and multi-stage buffer insertion for large-fanout nets.• Worked on Vt-swap decision logic and max-cap driven upsizing for buffer/inverter drivers and output buffering.

Education

• Indus International University (IIU), Una

  High School Diploma, Electrical, Electronics and Communications Engineering

• Indus International University (IIU), Una

  Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering

• RV VLSI

  Advanced Diploma in ASIC Design, Physical Design