Prerna Agarwal
BTECH EE ’26 NIT Surat |ASIC Aspirant| Seeking Front End Roles RTL DESIGN + VERIFICATION | Google Girl Hackathon 2025’ Semifinalist |VLSI system design ‘VSD RISC-SOC Tapeout
- Role
- Asic Design Verification at Prov Logic
- Location
- Surat, GJ, IN
- LinkedIn followers
- 500 followers
About Prerna Agarwal
Aspire to be a VLSI engineer with hands-on expertise in VLSI front-end flows, RTL design, and verification. Passionate about semiconductor innovation—accelerating AI/ML workloads through optimized digital hardware, SoC development, and computer architecture. Open to entry-level roles in VLSI, digital design, and chip verification.Gained practical experience designing UART protocols, DRAM controllers and RISC-V processor cores using Verilog/SystemVerilog in ModelSim and Xilinx Vivado.Eager to contribute to cutting-edge silicon solutions. let\'s connect on VLSI innovations, AI hardware, or tech builds! email - a••••••••@gmail.com
Experience
Asic Design Verification
Jan 2026 — Present · IN
Education
Sardar Vallabhbhai National Institute of Technology, Surat
Bachelor of Technology - BTech, Electrical engineering
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