Premanand Pathri
ASIC engineer PV at CISCO
- Role
- Asic Engineering Technical Leader at Cisco
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Premanand Pathri
Over 14 years of experience in defining and implementing Physical Verification methodology for next generation large and complex SoCs Strong acumen in Physical verification tasks including creating setup and scripts for DRC, LVS, DFM, Antenna and density checks, report generation, analysis, debugging and implementing fixes in the physical design database Conversant with the Custom IC design flow along with good understanding of layouts and overall backend tool flow Track record in performing physical verification on large hierarchical designs at chip level Deft in conducting various types of PV checks (LVS, DRC, DFY/DFM, lithography) at the chip/block level or chip tape-out experience with a track record of successful signoffs Expertise in physical verification to debug LVS/DRC issues at block level using Calibre tool suite Practiced with sign-off PDV tools like PDK Concepts, SVRF, Calibre and ICV
Experience
Asic Engineering Technical Leader
May 2026 — Present
Education
GIOE
Diploma, Electronics and Computer Science Engg.
2008 — 2011
Institution of Engineers of India (IEI), Kolkata
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
Skills
- Drc
- Design Rule Checking (Drc)
- Physical Design
- Vlsi
- C
- Physical Verification
- Perl
- Semiconductors
- Physical Verification (Drc/Lvs)
- Layout Versus Schematic (Lvs)
- Tcl
- Very-Large-Scale Integration (Vlsi)
- Cmos
- Lvs
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