Prem Sai

About Prem Sai

I am currently working as Staff Engineer – II, Device Design at iVP Semiconductor, where I aim to further contribute to innovation in semiconductor device design. As a Senior Project Engineer at SemiX, I focussed on semiconductor workforce development. My expertise in fabrication processes, process integration, electrical characterisation, and TCAD simulations was cultivated through practical experience at IIT Bombay’s state-of-the-art Nanofabrication Facility (IITBNF). I have since used these skills to contribute to the training and development of the workforce in novel semiconductor devices.During my Ph.D. tenure, I was selected for the Indian Nano-electronics Users Programme (INUP) project and received specialized training to mentor and train Ph.D. students. My role included providing guidance on various topics such as MOSFETs, GaN HEMT, NVMs, MEMS, and microfluidics, contributing to both INUP Phase II and Phase Alongside mentoring, I conducted my own research and played a key role in ensuring the successful delivery of project outcomes.In my Ph.D, I have worked on low-temperature Alumina for GFETs on Rigid (Silicon) substrates and also on flexible (Kapton) substrates.1. Seed layer engineering for crack-free sol-gel Alumina depositionon GFETs (MSSP 2023). DOI:10.1016/j.mssp.20•••••••82. Process Yield and Device Stability in Sol-gel Alumina Passivation layer-based GFETs TED 2023).DOI: 10.1109/ TED.20•••••••81.I Completed Masters in VLSI Design at SSN College of Engineering. My thesis titled \"Effect of Number of Fins on Input Impedance in MIGFET(Multiple Independent Gate FET) Using TCAD Simulations\"explored the FinFETs for RF applications. Additionally, the radiation performance of 4T, 6T, 7T, 8T and 10T MOSFET based-SRAMs have also been studied.1. Effect of Number of Fins on Input Impedance in MIGFETUsing TCAD Simulations(ICE-CCN, 2013). DOI: 10.1109/ICE- CCN.20••••••••42. SEU study of 4T, 6T, 7T, 8T, and 10T MOSFET-based SRAM using TCAD simulation (ICICES 2014). DOI: 10.1109/ ICICES.20•••••••19.

Experience

1. Staff Engineer -2-device Design

   Ivp Semiconductor

   Jul 2025 — Present · Mumbai, IN

Education

• Sri Venkateswara University

  Bachelor's Degree, Electrical, Electronics and Communications Engineering

  2006 — 2010

• Vignan Cooperative Junior college

  High School, Mathematics,Physics and Chemistry

  2004 — 2006

• Indian Institute of Technology, Bombay

  Doctor of Philosophy - PhD, Nanoelectronics

• SSN College of Engineering

  Master of Engineering (M.Eng.), VLSI Design

  2011 — 2013