Preeti Jha

About Preeti Jha

Pre‑Silicon Verification Engineer | Formal Verification (FPV)| UVM | High‑Speed ProtocolsExperienced Pre‑Silicon Verification Engineer with 7.5 years of expertise in validating complex SoC and IP designs across Ethernet controllers, GPUs, and interconnect architectures. I specialize in Formal Verification (FPV) and UVM‑based verification, driving end‑to‑end execution from test planning and environment development to coverage closure.I’m skilled at debugging RTL, assertions, and verification environments, and I work closely with cross‑functional design teams to ensure high‑quality silicon delivery. My background spans industry‑leading formal tools, high‑speed protocols, and modern verification methodologies.Core Skills & Expertise1. Verification Methodologies: Formal Verification, UVM2. Formal Tools: JasperGold (FPV, Connectivity, SEC, X‑Prop, Formal Coverage), Synopsys VC Formal, Synopsys Data Path Verification (DPV)3. Debug & EDA Tools: JasperGold, VC Formal, Verdi4. Languages: System Verilog, Python, C++, C5. Protocols: PCIe, Ethernet, AMBA (AXI, APB), CXLStrengths: Testbench development, test plan creation, coverage strategy and closure, assertion development, cross‑team collaboration

Experience

1. Mts Silicon Design Engineer

   AMD

   Feb 2025 — Present

   Formal Verification of Data Fabric unit/sub systems

Education

• BIT Sindri

  Bachelor of Technology - BTech, Electronics and communication engineering

  2010 — 2014

• Indian Institute of Technology, Kanpur

  Master of Technology - MTech, Signal Processing Communication and Network

  2016 — 2018