Preeti Chandra

About Preeti Chandra

Working with DFT team, expertise in VLSI design and digital testing. Core competencies include fault simulation, scan design, ATPG,SAF/TDF, with hands-on experience using industry-leading tools such as Mentor Graphics Tessent and Cadence MODUS. Contributions focus on optimizing testing methodologies, enabling efficient circuit validation, and ensuring robust design-for-test workflows. Passionate about advancing the field of digital electronics, the team collaborates to implement innovative solutions in combinational and sequential circuit testing, boundary scan fundamentals. Dedicated to refining simulation processes through timing and non-timing analysis, empowering effective end-to-end design verification.

Experience

1. Staff Engineer

   Qualcomm

   Jan 2025 — Present · Bengaluru, IN

Education

• Banasthali vidhyapith

  M.tech, VLSI Design

  2014 — 2016

• Bishop Conrad Sr. Sec. School

  12th

  2008 — 2009

• SRMSWCET

  Bachelor of Technology (B.Tech.), Electronics and Communications Engineering

  2009 — 2013

• Sacred Hearts Sr. Sec. School

  10th

  2006 — 2007

Skills

• Cmos
• Perl
• Very-Large-Scale Integration (Vlsi)
• Microsoft Excel
• Powerpoint
• C++
• Automation
• Verilog
• Shell Scripting
• Windows
• Field-Programmable Gate Arrays (Fpga)
• Vhdl
• Cadence Virtuoso
• Microsoft Office
• C
• Programming
• Physical Design
• Application-Specific Integrated Circuits (Asic)
• Linux
• Semiconductors
• Rtl Verification
• System Verilog
• System on a Chip (Soc)
• Digital Electronics
• Engineering
• Systemverilog
• Microsoft Word
• Electronics