Preethi Kumar

About Preethi Kumar

I am pursuing a Master of Science in Electrical Engineering at Syracuse University, specializing in VLSI, Embedded Systems, Digital Communication, Digital Electronic Circuits, and System-on-Chip Design. My undergraduate degree in Electronics and Communication Engineering from Visvesvaraya Technological University provided me with a strong foundation in electronic and communication principles.I gained professional experience through an internship with QSpiders Campus Connect (Test Yantra Software Solutions India Pvt Ltd), where I worked on full-stack development using Python, SQL, and Django. I led requirement analysis, designed and optimized dynamic web applications, and collaborated with cross-functional teams to deliver scalable solutions.My technical expertise spans programming (C, C++, Python, Java, SQL), hardware description languages (Verilog, VHDL), and simulation/design tools (MATLAB, ModelSim, CAD). I am passionate about applying my skills to VLSI chip design and embedded system innovations, bridging the gap between hardware and software.I am eager to connect with professionals and explore opportunities where I can contribute my knowledge, problem-solving skills, and enthusiasm to impactful technology-driven projects.

Experience

1. Digital Asic Front-end (Rtl) Design Engineer

   Honeywell Technologies

   Dec 2025 — Present · US

   Designed synthesizable RTL modules using SystemVerilog and Verilog for safety-critical ASIC subsystems, contributing to a 20% improvement in design performance across multi-clock architectures. • Developed micro-architecture specifications and parameterized RTL blocks aligned with full ASIC design flow, reducing redesign iterations by 25% during design reviews and integration cycles. • Executed CDC and RDC analysis using SpyGlass, resolving domain crossing violations, improving functional stability and silicon readiness before synthesis stages. • Performed RTL synthesis using Synopsys Design Compiler and Cadence Genus, achieving timing closure on 95% of critical paths through optimized constraint implementation and design refinement. • Built and enhanced verification environments with SystemVerilog testbenches and assertions, increasing functional coverage by 30% and accelerating bug detection during RTL simulation. • Conducted detailed debug and waveform analysis using QuestaSim, VCS, and Xcelium, reducing verification turnaround time by 35% across complex integration test scenarios. • Defined and validated SDC constraints for multi-clock designs, supporting front-end timing closure and improving STA convergence. • Automated regression workflows using Python, TCL, and Shell scripting, decreasing manual simulation effort by 40% and improving engineering productivity.

Education

• Syracuse University

  Master of Science - MS, Electrical and Electronics Engineering

• Visvesvaraya Technological University

  Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering