Preetam Meharwade

About Preetam Meharwade

Design Engineering Group Director with 20+ years specializing in DDR/LPDDR AMS circuit design—owning programs end‑to‑end from spec/architecture through tape‑out and silicon bring‑up at 14.4 Gbps and beyond. I’ve delivered 30+ silicon‑proven test chips and a greater number of successful customer programs, while leading 50+ direct and ~30 matrix engineers. My leadership is hands‑on, data‑first, and scalable: set crisp design intent, unblock fast, enforce SI/PI‑centric decisions, and codify best practices so teams execute independently. I partner closely with PHY‑RTL, SI/PI, package, DFT, Firmware, validation, and customer engineering teams to keep schedules predictable and risks visible. I’ve owned setbacks—tackling failures head‑on with transparent root‑cause analysis and optimal customer solutions—then embedding those learnings to train project leads and strengthen delivery discipline. My focus is pragmatic execution and cross‑functional alignment—yielding predictable schedules and silicon‑proven DDR/LPDDR performance.

Experience

1. Design Engineering Group Director

   Cadence

   Jan 2026 — Present · Bengaluru, IN

Education

• Adichunchanagiri Institute of Technology (AIT) Chikmagalur. University: VTU Belgaum

  BE, Electronics and Communication

  1999 — 2003

• PG-Centre, Visveswariah Technological University Belgaum

  M-Tech, VLSI Design and Embedded Systems

  2003 — 2005

Skills

• Drc
• Verilog
• Application-Specific Integrated Circuits (Asic)
• Physical Verification
• Technical Documentation
• Monte Carlo Simulation
• Unix
• Simulations
• Very-Large-Scale Integration (Vlsi)
• Lvs
• I2c
• Gpio
• Io Circuit Design
• Arm
• Io Layout
• Pls
• Eldo
• System on a Chip (Soc)
• C
• Vlsi
• Cadence Virtuoso
• Circuit Design
• Standard Cell
• Design Rule Checking (Drc)
• Cadence Spectre
• Embedded Systems
• Semiconductors