Preeta Katiyar
Rtl Design and Verification Engineer @SiPearl
Aschaffenburg, DE
EMAILS
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Jun 2022 — Present
Rtl Design and Verification Engineer @SiPearl
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EDUCATION
2012 — 2014
Banasthali Vidyapith
Master of Technology - MTech
2006 — 2010
Rajasthan Technical University, Kota
B.Tech
SKILLS
System on a Chip (Soc)Rtl DesignEmbedded SystemsAnalog Circuit DesignModelsimVerilogTclAsicVlsiI2cMemory Layout DesignFpgaSpiceCadence VirtuosoDigital ElectronicsPhysical DesignLeonardo SpectrumField-Programmable Gate Arrays (Fpga)Mixed SignalMicrocontrollersSocAnalogLow-Power DesignXilinxCadenceSpiMatlabCmosXilinx IseVhdl
ABOUT PREETA KATIYAR
Experienced RTL design engineer expertise in ASIC design, SoC development, and digital…
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