Prayag Patel

About Prayag Patel

I lead the engineering of the world’s most efficient high-performance silicon. As a 23-year Qualcomm veteran with 30+ years in the field, I govern a global organization of 500+ engineers advancing the Adreno GPU roadmap through the industry’s first 2nm implementations.• Directed the successful tape-out of several GPU, DSP, CPU cores and SOCs.• Strategic oversight of the RTL-to-GDS lifecycle across Mobile, PC, XR, Wearables and Automotive.• Engineered custom physical implementation strategies that surpass global PPA standards with 15 issued US patents.• Expanded global engineering capabilities to support the ever expanding computing roadmap

Experience

1. Vice President of Engineering

   高通

   Jan 2003 — Present · San Diego, CA, US

   I lead the engineering of the world’s most efficient high-performance silicon. As a 23-year Qualcomm veteran with 30+ years in the field, I govern a global organization of 500+ engineers advancing the Adreno GPU roadmap through the industry’s first 2nm implementations.• Directed the successful tape-out of several GPU, DSP cores and SOCs.• Strategic oversight of the RTL-to-GDS lifecycle across Mobile, PC, XR, Wearables and Automotive.• Engineered custom physical implementation strategies that surpass global PPA standards with 15 issued US patents.• Expanded global engineering capabilities to support the expanded roadmap2012 - Present- Responsible for all aspects of the physical implementation of the QCOM Adreno GPU cores (RTL -> GDS). This includes synthesis, P&R, low power design, power delivery, clocking, process technology and customized IP solutions. Successfully delivered numerous semi-custom GPU solutions that are optimized from a power, area and performance perspective.20•••••27 year)- Lead the QCOM Standard cell libraries and custom cell library teams focussed on building best in class foundation IP for all the QCOM SOCs. Emphasis on low power, high speed and low area SOC designs.20•••••51 year)- CAD/Methodology/Flow development for transistor level design. This work spanned timing analysis, formal verification, electrical checks, SI analysis etc.20•••••41 year)- Part of the Qualcomm DSP custom circuit design team responsible for delivering the first semi-custom DSP solution with significant power, performance and area gains compared to prior solutions.

Education

• JAI HIND COLLEGE, MUMBAI

  High school, Electrical and Electronics Engineering

  1988 — 1990

• University of California, Davis

  Master of Engineering - MEng, Computer Engineering

• Thadomal Shahani Engineering College

  BE, Electrical and Computer Engineering

  1990 — 1994

• St. Mary's School ICSE Mumbai

  ICSE

  1977 — 1988

Skills

• Debugging
• Silicon
• Systemverilog
• Vhdl
• Semiconductors
• Application-Specific Integrated Circuits (Asic)
• Modelsim
• Verilog
• Vlsi
• Hardware Architecture
• Serdes
• Signal Integrity
• Primetime
• Mixed Signal
• Circuit Design
• Ic
• Soc
• Firmware
• Logic Design
• Logic Synthesis
• Physical Design
• Eda
• Functional Verification
• Fpga
• Asic
• Pll
• Very-Large-Scale Integration (Vlsi)
• Digital Signal Processors
• Analog Circuit Design
• Rtl Design
• Power Management
• Timing Closure
• Formal Verification
• Tcl
• Analog
• Rf
• Semiconductor Industry
• Pcie
• Integrated Circuit Design
• Microprocessors