Praveen Vijayan

About Praveen Vijayan

Hello, I am a highly skilled VLSI chip design professional with over 15 years of experience in the industry. Throughout my career, I have focused on Design for Excellence (DFX) and VLSI Testing techniques for a diverse range of high-performance, low-power, and highly integrated Server SoCs, DSPs, FPGAs, and mobile processors.Some of my key areas of expertise include:Memory BIST Architecture: I am an expert in Memory Built-In Self-Test (MBIST) insertion and test solutions, memory fault modeling, test algorithm development, test planning, and memory repair solutions, including Built-In Redundancy Analysis (BIRA) and Built-In Self-Repair (BISR) at both RTL and gate level.DFT: I have a strong background in DFT features such as Scan Insertion, Compression techniques, On-Chip Clocking (OCC), Power-aware DFT Implementation, Automatic Test Pattern Generation (ATPG), Coverage Analysis, and simulations.IP DFT and RTL Integration: I possess hands-on experience in DFT and rtl integration of various IPs such as CPUs, GPUs, Modems, Videos, and Displays, ensuring robust testability and efficient debugging.Timing Constraints and ECOs: I have worked extensively on test mode timing constraints and provided effective timing fixes and corrective actions to address timing violations and Engineering Change Orders (ECOs).Pre and Post-Silicon Validation: I am proficient in generating, simulating, validating, and providing debug support to Automatic Test Equipment (ATE) for both Scan and BIST patterns.Silicon Debugging and Analysis: I have a proven track record of identifying functional and structural bugs on ATE and boards, as well as conducting failure analysis, yield analysis, and implementing VVM and TT improvement strategies. Advantest 93K Test Solutions: I have hands-on experience in utilizing the Advantest 93K test platform for timing and shmoo analysis.Reliability Engineering: I am well-versed in developing test programs and hardware for Reliability Engineering tests such as High-Temperature Operating Life (HTOL), Temperature Humidity Bias (THB), Electrostatic Discharge (ESD), Latch-up, and Electromagnetic Interference (EMI).I am passionate about pushing the boundaries of VLSI chip design, embracing new challenges, and contributing to cutting-edge innovations in the semiconductor industry. I am open to networking opportunities, collaboration, and discussing potential projects where my expertise can be applied effectively.Feel free to connect with me to explore mutual interests or discuss any opportunities for collaboration or professional growth.

Experience

1. Director of Engineering - Dft

   Microsoft

   Sep 2024 — Present · Bengaluru, IN

   Leading DFT & DFD Teams for Cloud Computing Development Organization in IDC

Education

• Cochin University of Science and Technology

  B-tech, Electronics and communication

• National Institute of Technology Hamirpur-Alumni

  Master of Technology (MTech), VLSI Design