Praveenkumar S

About Praveenkumar S

14 years of experience in design verification of various IP\'s, Subsystem and SoC\'s-> Verification Sign-off for Debug Sub-System modules for high performance eSSD and cSSD flash controller Soc with multi Processors (35 CPU) architecture which includes HW & FW trace events, CPU Smart events, ARCOH trace events, multiple HEB (Hardware Event Bridge), FEB (FW Event Bridge), JTag Chain access, NG_SET (System Event Tracer) connected to Internal TBRAM and External Debugger through HSSTP (High Speed Serial Transfer Protocol) PCie Gen1 | Gen2 | Gen3 1xLane, 4xLane support for trace data transfer-> Gate Level Simulation closure of all Debug IP\'s-> Testbench integration & bringup, SOH, ARCOH, FEB, HEB, SET, SoC system level end to end scenario creation for Debug SS, HSSTP model integration & Scoreboard updates for event comparisions-> Mem_task updates for all interleaving memories and MBOX updates-> Experienced in UVM based testbench development and UVC creation from scratch, System Verilog, Verilog knowledge-> Worked on VIP development for serial RapidIO protocol GEN1 | GEN2 | GEN3 Logical layer, Transport Layer, PHY layer maximum speed supported is 160 Gbps 16 Lane support with UVM testbench-> Experienced in SRIO-Serial Rapid Input Output serial interconnect protocol, worked in all three layers – Logical layer, Transport layer, Physical layer - Mobiveil -> Experienced in RAB – RIO_AXI_BRIDE - Mobiveil -> Experienced in Formal verification using Jasper Tool and Questa formal-> Experienced in code and function coverage-> Experienced in UVM component, Register model and Functional coverage development.Experienced in Test case creation and regression maintenance. Proficient Knowledge in SRIO, TileLink, OTP macro, AXI, APB, RAM, SPI, UART, I2C and Router protocols.

Experience

1. Principal Engineer

   WD

   May 2022 — Present · Bengaluru, IN

Education

• Anna University of Technology. Paavai College of Engineering

  Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering

  2007 — 2011

Skills

• Vlsi
• Field-Programmable Gate Arrays (Fpga)
• Uvm
• Rtl Design
• Perl Script
• Verilog
• Functional Verification
• Open Verification Methodology
• Fpga
• Perl
• Asic
• Modelsim
• Soc
• Xilinx
• Systemverilog
• Ovm