Praveen Komatineni

Validation Engineer @Righthand Technologies, Inc

Chicago, IL, US

Developed and executed comprehensive validation plans for secure embedded processor subsystems, focusing on RTL power-awareness and timing closure in SystemVerilog-based designs.•Collaborated with cross-functional teams including mathematicians, cryptographers, and physicists to identify and validate hardware-level security vulnerabilities, including side-channel attack vectors.•Authored detailed validation reports and documentation to clearly communicate complex security and VLSI validation concepts to both technicaland non-technical stakeholders.•Validated micro-architectural features such as pipeline control logic, FSMs, and datapath sharing to ensure correct, secure, and glitch-free functionality across edge cases.•Verified security-focused firmware and RTL interactions, validating robustness against timing-based and leakage-based attacks in a pre and post-silicon environment.•Performed synthesis-aware validation using results from Synopsys Design Compiler, ensuring area and performance constraints met with over 97% utilization efficiency.•Conducted Clock Domain Crossing (CDC) analysis using SpyGlass CDC; validated fixes for asynchronous resets and FIFO boundary issues in multiclock secure SoC environments.•Assisted in post-silicon bring-up and debug, including scan chain validation, waveform analysis, and hardware-level security validation on test silicon.•Supported static timing analysis validation using PrimeTime and Innovus; incorporated process and thermal variation considerations for robust silicon performance.•Automated security-aware regression environments and RTL build flows using TCL and Python, enabling nightly runs with integrated design rule and security compliance checks.