Praveen Waliitagi

Fe Integration Engineer @Apple

San Jose, CA, US
MOBILE NUMBERS
+91 *********19

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WORK HISTORY

Oct 2022 — Present

Fe Integration Engineer @Apple

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Cupertino, CA, US

EDUCATION

2006 — 2010

Visvesvaraya Technological University

B.E, Electronics and Communication

2014

San José State University

Master's Degree, Electrical and Electronics Engineering

SKILLS

AsicSocLogic SynthesisAmbaComputer ArchitectureSystem VerilogVhdlSystem on a Chip (Soc)Perl AutomationAmba AhbApplication-Specific Integrated Circuits (Asic)IcCIntegrated Circuit DesignMicrocontrollersPerlEmbedded SystemsRtl DesignDigital DesignSystemverilogVerilogStatic Timing AnalysisFormal VerificationVery-Large-Scale Integration (Vlsi)Vlsi

ABOUT PRAVEEN WALIITAGI

Graduate Student at San Jose State university specializing in VLSI Digital Design. Specialties: I’m skilled in RTL design (Verilog and System Verilog) and scripting language PERL. Have good knowledge of computer architecture. Have worked on tools like “Atrenta spyglass” for lint check, “Mentor graphics 0-in” for CDC, “ Synopsys Design Compiler” for synthesis,and “Cadence LEC” tool for formal verification.Interests:Digital Design, RTL (SV Verilog) Linting, CDC, Synthesis, STA, FV. SOC constraint management tools.IP Verification.

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Praveen Waliitagi — Fe Integration Engineer at Apple in San Jose, CA, US | Unifers