Praveen R K

About Praveen R K

4+ years of experience in the ASIC/SOC verification in the VLSI industry. Currently Working in Cisco Systems as Senior Hardware Engineer.Current work experience in System Verilog with UVM Methodology along with Reference Model development in C++ for functional and Coverage driven Verification of complex ASICs in Networking Domain.Worked on SoC and complex Module/IP verification projects in System Verilog, UVM, VMM Methodology.Domains or IPs worked on include Ethernet, USB 3.0, uart, gpio, wdt, amba bus protocols like APB.Worked on Gate level Simulations and SDF simulations.Work experience in the industry include design and coding of verification environment for different modules and SoC in system verilog, using UVM, VMM methodology, Reference Model development in C++, Identifying and Writing functional coverage, identifying and writing test cases to check the functionality of the DUT and achieving coverage goals.Interested in working on verification of complex IPs, SoC verification using latest verification methodologies and achieving the verification goals to meet the deadline through a smart and convincing approach and increase the productivity.

Experience

1. Senior Asic Engineer

   NVIDIA

   Dec 2014 — Present

   Working on Modem-Chip verification in System Verilog, UVM.

Education

• Indian Institute of Management Mumbai

  Bachelor's degree, Electronics and Communications Engineering

  2006 — 2010

Skills

• System Verilog
• Soc
• Front End Verification
• Apb
• Usb
• Systemverilog
• Wdt
• Identifying and Coding Test Cases
• Verification Environment Design and Coding
• Vlsi
• Reference Model Development
• Usb3.0
• Hardware
• Gpio
• Uvm
• System Verilog Assertion
• Vmm
• Module Level and Soc Level Verification
• C
• Asic
• Functional Verification
• Uart
• Usb 3.0
• Verilog
• Switches
• Amba Ahb
• C++
• Ethernet