Praveen Mehrotra

About Praveen Mehrotra

12+ yrs in ASIC Verification Experience in development of System Verilog based Testbench, Verification Plan, and Test Case Coding. Gate level simulation. UPF verification. SOC verification Experience in writing RTL models in Verilog HDL and in System Verilog Experience in development of Verification IPs and BFMs Experience in using industry standard EDA tools for the front-end design and verification Experience in using 3rd Party design IPs and Verification IPs Experience in Standard Verification methodologies such as UVM & OVM Knowledge of Low Power basic and UPF Good digital Electronics knowledge Experience in Protocols such as AMBA bus (APB and AXI3/AXI4),RAPID I/O, USB3.0 Basic, JTAG, I2C, SPI, UART etc. Coverage plan development, Functional Coverage and Code Coverage analysis and improvement, Running Regressions, test case fix and debugging the issues. Good understanding of Scripting: Shell, Perl, Tickle

Experience

1. Project Lead

   Sevitech

   Jan 2022 — Present · MY

Education

• Shivaji University

  Post Graduation Diploma; B.E, VLSI; Electronics & Communications Engineering

• Centre for Development of Advanced Computing (C-DAC)

  DVLSI, VLSI

  2005 — 2006