Praveen Maddu
Associate Director, Design Verification Engineering
- Role
- Associate Director at Samsung Semiconductor
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Praveen Maddu
HDLs : Verilog HVL : SystemVerilogVerification Methodology : UVM Tools : Synopsys VCS, NCSim, Verdi, VManagerDomain : ASIC/SoC Verification.Knowledge : Code Coverage, Functional Coverage, Linting. Scripting Languages : Perl,Tcl.Version Control : svn,cvs,Perforce
Experience
Associate Director
Mar 2026 — Present · Bengaluru, IN
Education
Surya Junior College
Intermediate, MPC
2005 — 2007
Sri Vasavi Engineering college
Bachelor of Technology, Electrical & Electronics Engineering
2007 — 2011
Surya High School
SSC
2000 — 2005
Skills
- Rtl Design
- Functional Verification
- Vhdl
- Simulations
- Code Coverage
- Verilog
- Universal Verification Methodology (Uvm)
- Formal Verification
- Xilinx
- Systemverilog
- Application-Specific Integrated Circuits (Asic)
- Physical Verification
- System Verilog
- Tetramax
- Ovm
- System on a Chip (Soc)
- Timing Closure
- Perl Scipt
- Semiconductors
- Dft
- Tcl
- Logic Synthesis
- Logic Design
- Rtl Verification
- Vlsi
- Ncsim
- Rtl Coding
- Fpga
- Asic
- Uvm
- Amba Ahb
- Soc
- Integrated Circuit Design
- Modelsim
- Perl
- Eda
- Vmm
- Primetime
- Static Timing Analysis
- Digital Electronics
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