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Praveen Kumar Perugu

Design Verification Engineer at BITSILICA

Role
Design Verification Engineer at BITSILICA
Location
Hyderabad, IN
LinkedIn followers
500 followers
EngineeringView LinkedIn profile

About Praveen Kumar Perugu

VLSI Design and Verification Engineer with a demonstrated history of working in the BITSILICA PVT LTD. Skilled in Universal Verification Methodology (UVM), SystemVerilog, Verilog, Debugging and Functional Verification.

Experience

  1. Design Verification Engineer

    BITSILICA

    Oct 2019 — Present · Hyderabad, IN

Education

  • QIS College of Engineering & Technology, Vengamukkapalem (Village), Pondur Road, Ongle(M),PIN-523 272.(CC-49)

    Bachelor's degree, Electrical, Electronics and Communications Engineering

    2011 — 2015

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Praveen Kumar Perugu — Design Verification Engineer at BITSILICA in Hyderabad, IN | Unifers