Praveen Hunchikatti

About Praveen Hunchikatti

Around 5+ years of Function Design Verification experience.Specialities- Functional Verification using System Verilog and UVM methodologies including the design of constrained random test benches- Experience in test planning, code coverage and functional coverage metrics and system verilog assertions Proficient in System Verilog, Verilog, Perl, C and shell scriptingSkillset:Programming Languages: System Verilog, Verilog, Perl, C, SpiceEDA Tools: Synopsys DVE, VCS, Cadence Virtuoso, Encounter, Tetra-MAX, Design Vision, Prime Time, Liberty NCX Cadence Pspice, LT Spice, Hspice, Model SIM, Simple ScalarSoftware: Laboratory Equipment: Oscilloscope, Spectrum Analyzer, Logic Analyzer

Experience

1. Verification Engineer

   Samsung Electronics

   Jul 2018 — Present · Austin, TX, US

Education

• The University of Texas at Dallas

  Master of Science (M.S.), Digital Systems

  2011 — 2013

• Ramaiah Institute Of Technology

  B E, Electrical Electronics

  2004 — 2008

Skills

• Analog Circuit Design
• Pspice
• Hspice
• Verilog
• Vhdl
• Cadence Virtuoso
• Model Sim
• Synopsis
• C
• Matlab
• Mathcad
• Mixed Signal
• Power Supply Design
• Digital Design
• Circuit Simulation
• Vlsi
• Cadence
• Do-160
• Simulations
• Systemverilog
• Perl
• Modelsim
• Spice
• Integrated Circuit Design
• Analog
• Digital Electronics
• Pcb Design
• Shell Scripting
• Application-Specific Integrated Circuits (Asic)