Praveen Durga
Executive Director of Engineering, SoC Design at Synopsys Inc
- Role
- Executive Director of Engineering, Soc Design at Synopsys Inc
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Praveen Durga
High performing strategic leader with 25+ years of experience in managing SoC and IP Design R&D teams, championing processes and quality with proven track record of delivering multiple SoCs, Subsystems and IPs.Collaborative leader connecting product strategy, technology roadmap, planning and execution with a keen understanding of business and market dynamics that has led to the Tapeout of 14+ Consumer and Automotive MCUs generating $1B+ of lifetime revenue.Driven focused initiatives towards NPI Design Quality with objective of Zero-Defect and First Time Right designs with improved efficiency through Design Post Mortems, Lessons Learnt, Continuous Improvement, Kaizens and Hoshins. Quality Site Leader for ISO9001/TS16949 Audits since 2008.Additional Qualifications attained during the career - PhD (Electronic Engineering) from University of Bath, England, UK and Executive MBA from Faculty of Management Studies, University of Delhi, IN.Ability to develop strategic long-term partnerships with customers, foundry partners, packaging, testing, Design services and EDA vendors. Communicate effectively with all levels of decision makers and stake holders across globe.Currently working as Director – Automotive SoC Frontend RTL Design and Emulation at NXP Austin. Have worked in varied capacities throughout my career, gaining adaptability and expertise in:o SoC Requirement Management - DOORso SoC/IP Architecture, Micro-Architecture and Design Reuse strategieso SoC Integration - Digital and Mixed Signal IPs, PowerPC, ARM coreso Automotive Functional Safety Architecture and Management (Certified Automotive Functional Safety Professional by SGS-TÜV Saar ID: 2674)o Digital Design, RTL Design (Verilog, VHDL), Automation Tools/Flows/Methodologieso SoC/IP Design Processes, KPIs, Metrics, Configuration Managemento SoC/IP Verification, FPGA Emulation and Silicon Validation Debug and supporto Design Quality – ISO9001/TS16949, Risk Analysis, Design FMEA, Zero-Defect, Defect RCA (5-Why, 8-D), Best Practices, Continuous Improvement, Lean Managemento Project Feasibility and Planning, Third-Party IP / Tools Evaluation and Procuremento Resource Management, SoC Execution and Interaction with global customers, stakeholders and weekly presentations to Leadership.o Team Performance Management, Hiring Plans, Interviews, InternsWork Authorizations: USA (Permanent Resident - Greencard), India
Experience
Executive Director of Engineering, Soc Design
Dec 2022 — Present · Austin, TX, US
Education
Jamia Millia Islamia
B.Tech, Electronics and Communications Engineering
University of Bath
PhD, Research on SoC Design Methodologies
Faculty of Management Studies - University of Delhi
Master of Business Administration (M.B.A.), Executive MBA
Skills
- Debugging
- Emulation
- Uart
- Processors
- Microcontrollers
- Low-Power Design
- Integrated Circuit Design
- Microprocessors
- Functional Verification
- Management
- Ic
- Rtl Coding
- Application-Specific Integrated Circuits (Asic)
- Change Management
- Embedded Systems
- Eda
- System on a Chip (Soc)
- Leadership Development
- Timing Closure
- Ethernet
- Semiconductors
- Verilog
- Soc
- Formal Verification
- Rtl
- Logic Design
- Very-Large-Scale Integration (Vlsi)
- Electronics
- Fpga
- Asic
- Vlsi
- Digital Electronics
- Rtl Design
- Technical Project Leadership
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