Praveen Bhat
Senior staff Engineer/IC Packaging/Advanced Packaging
- Role
- Silicon Packaging Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Praveen Bhat
Ability to create and design packages and PCB that meet the semiconductor industry\'s electrical, thermal, and mechanical requirements.Ability to design and optimize the placement and routing of the interconnects, bond pads, and power/ground planes.Ability to work collaboratively with other design team members, including IC designers, system architects, and mechanical engineers, to ensure the package meets the system requirements.Manage the schedule and resources required for package development, including coordinating with vendors and suppliers.Understanding of industry standards, such as JEDEC and IPC, and the ability to incorporate them into the package design.Understanding and hands-on with, Wafer-level chip-scale packaging (WLCSP), Chiplets,2.5D,3D stacking, HBM,EMIB, Substrate materials/PCB Design experience with multilayer HDI.Tools Cadence, Altium,Mentor Graphics
Experience
Silicon Packaging Design Engineer
Feb 2026 — Present · Bengaluru, IN
Education
Singhania University
Bachelor of Physics, Physics
Department of technical Education-Karnataka
Diploma , Electrical, Electronics and Communications Engineering
2005 — 2008
Skills
- Analog
- C++
- Microcontrollers
- Allegro
- Pcb Design
- C
- Orcad
- Embedded Systems
- Eda
- Altium Designer
- Cadence
- High Speed Design
- Electronics
- Vlsi
- Signal Integrity
- Schematic Capture
- Embedded Software
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